1. Field of the Invention
The present invention relates to a wiring board such as a tape carrier substrate used for a chip-on-film (COF) and a method for manufacturing the same, and also relates to a semiconductor device including a semiconductor element bonded to the wiring board.
2. Description of Related Art
As one type of package modules using a film substrate, a COF has been known. FIG. 5 is a partial cross-sectional view showing an exemplary COF. The COF includes a semiconductor element 6 mounted on a tape carrier substrate made of a flexible insulating film base 1, which is protected by an encapsulation resin 7. The COF mainly is used for a driver for driving a flat panel display and the like.
The main constituents of the tape carrier substrate include the insulating film base 1, conductive wirings 2 formed on the face of the film base 1 and protrusion electrodes (bumps) 3 formed on the conductive wirings. A metal plated coating 8 is formed on a part of the conductive wirings 2 and the bumps 3, if necessary, and a solder resist layer 9 as an insulating resin is formed on the other portion of the conductive wirings 2. In general, polyimide is used as the film base 1, and copper is used as the conductive wirings 2.
The conductive wirings 2 are connected with electrode pads 10 on the semiconductor element 6 via the bumps 3. As the general connection method, after an encapsulation resin is applied at a portion on the film base 1 where the semiconductor element is to be mounted, the electrode pads 10 of the semiconductor element 6 are opposed to the bumps 3 of the tape carrier substrate, and ultrasonic energy, heat and pressure are applied thereto. FIG. 6 is a plan view of an exemplary tape carrier substrate prior to the mounting of a semiconductor element, and FIG. 7 is a plan view of an exemplary semiconductor element 6. The bumps 3 of the tape carrier substrate are formed at positions corresponding to the electrode pads 10 of the semiconductor element 6 (see JP 2004-327936 A, for example).
On the periphery of the film base 1, a feeding conductive pattern 4 is formed. In the vicinity of the boundary between the conductive wirings 2 and the feeding conductive pattern 4, a cutting region 5 is formed. At the time of the formation, the conductive wirings 2 and the feeding conductive pattern 4 are connected and electricity is fed to the conductive wirings 2 via the feeding conductive pattern 4 during the electroplating step for forming the bumps 3. After the formation of the bumps 3, the cutting region 5 is formed, whereby the conductive wirings 2 and the feeding conductive pattern 4 are separated electrically.
The following describes a method of manufacturing a conventional tape carrier substrate, with reference to FIGS. 8A to 8C. FIGS. 8A to 8C are plan views showing manufacturing steps of a conventional tape carrier substrate, FIG. 8A to FIG. 8C showing plan views of the tape carrier substrate during the respective manufacturing steps.
Firstly, with respect to a film substrate 1 on which a plurality of conductive wirings 2 and a feeding conductive pattern 4 used for electroplating are connected electrically as shown in FIG. 8A, electroplating is carried out via the feeding conductive pattern 4, whereby bumps 3 are formed as shown in FIG. 8B.
Next, as shown in FIG. 8C, a cutting region 5 is formed, whereby the conductive wirings 2 and the feeding conductive pattern 4 are separated electrically. Thereby, a tape carrier substrate is obtained on which the bumps 3 are formed on the conductive wirings 2 that are electrically independent of one another.
Note here that a connection terminal portion 11 is a part of the conductive wirings 2 and is used for the connection with an external component such as a flat panel. In general, the conductive wirings 2 and the feeding conductive pattern 4 are separated electrically by punching the tape carrier substrate at a region other than the connection terminal portion 11.
Further, although not illustrated, a metal plated coating or solder resist may be formed at the correct timing during the process of FIG. 8A to FIG. 8B or after the process.
Because of various panel sizes, definitions and the like of recent flat panel displays, the number of connection terminals of a COF as a semiconductor device with a flat panel, i.e., the number of output terminals of a semiconductor device also has been diversified. Accordingly, if different semiconductor elements are prepared according to semiconductor devices having respective numbers of output terminals, the types of the semiconductor elements will increase, so that the developing cost will increase and managing the mass production of such semiconductor elements will become complicated.
For that reason, in the case of semiconductor devices required to have similar electrical functions, the efficiency of the production will be improved when a common semiconductor element is used, even for the semiconductor devices having different output terminal numbers. However, when a common semiconductor element is used, if the number of connection terminals with an external component (flat panel) of a semiconductor device is less than the number of electrode pads of the semiconductor element, the following problems would occur.
FIG. 9 shows an exemplary tape carrier substrate where the number of connection terminals of a semiconductor device with an external component is less than the number of electrode pads of a semiconductor element. The number of bumps 3 corresponds to the number of the connection terminals with an external component. As shown in this drawing, since the number of the connection terminals with an external component of the semiconductor device is less than the number of the electrode pads of the semiconductor element, the bumps 3 cannot be arranged uniformly, where intervals between the bumps 3 are increased at a portion where the bumps 3 are not disposed.
In the case where the bumps 3 cannot be formed at constant intervals in such a way, the growth degree of the plating for forming the bumps 3 tends to vary because of the nonuniformity of the arrangement of the bumps 3. This causes a stress concentration at a certain portion during the mounting of the semiconductor element, thus increasing the possibility of connection malfunction.
Meanwhile, as shown in FIG. 9, the conductive wirings 2 are designed to have constant intervals at the connection terminal portion 11 for connection with the external component, which is for increasing the efficiency of the use of the area. Thus, even when an attempt is made to arrange the bumps 3 at constant intervals by forming additional bumps (dummy bumps) corresponding to electrode pads not used on the semiconductor element (dummy electrode pads), it is difficult to design conductive wirings for forming such dummy bumps thereon to be connected with the feeding conductive pattern.